Semiconductor processing employs techniques for depositing layers, removing layers, defining features (e.g., etch), preparing layers (e.g., cleans), doping or other processes that do not require the formation of a layer on the substrate. In addition, similar processing techniques apply to the manufacture of integrated circuits (IC) semiconductor devices, flat panel displays, optoelectronics devices, data storage devices, magneto electronic devices, magneto optic devices, packaged devices, and the like. As feature sizes continue to shrink, improvements, whether in materials, unit processes, or process sequences, are continually being sought for the semiconductor manufacturing processes. However, semiconductor companies conduct R&D on full wafer processing through the use of split lots, as the processing systems are designed to support this processing scheme. This approach has resulted in ever escalating R&D costs and the inability to conduct extensive experimentation in a timely and cost effective manner.
With regard to wet processing techniques utilized in the semiconductor industry, current research and development techniques are unable to efficiently evaluate the variation of process parameters, materials, process sequences, etc., in an efficient manner. Even if a system was available to more efficiently evaluate processes and materials, the system should be able to mimic the conditions for full wafer processing so that the processes can scale if the system operates on a smaller scale.
Thus, an improved technique for accommodating the evaluation of multiple different process variations on a single substrate is provided to more efficiently evaluate the viability of different materials, unit processes, or process sequences.